1. Field of the Invention
This invention relates to a hysteresis input buffer and, more particularly, to a hysteresis input buffer for providing an adequate noise margin and a high speed response depending on the characteristics of an input signal.
2. Discussion of Related Art
Conventional input buffers are used in semiconductor integrated circuits to control the transfer time or voltage level of input signals externally received from an outside source. The conventional input buffers transform the TTL (Transistor Transistor Logic) levels of the input signals into CMOS (Complementary Metal-Oxide Semiconductor) levels for use in the integrated circuits.
The conventional input buffers are generally constructed by inverters connected in multistages, and especially by CMOS inverters each formed with a PMOS transistor and an NMOS transistor connected in series between a supply voltage terminal and the ground. If there is an even number of CMOS inverters connected in series (forming an even number of stages), it is possible to transform the voltage level of the input signals to a desired level without inverting the input signals, depending on the driving capabilities of the CMOS inverters. If an odd number of the CMOS inverters are connected in series (forming an odd number of stages), the input signals are inverted by the CMOS inverters.
Although the conventional input buffers can be structured in many different ways, two buffer types--inverter type CMOS input buffers and hysteresis input buffers--are generally used. The inverter type CMOS input buffers are CMOS input buffers connected in two stages and the hysteresis input buffers are inverter type CMOS input buffers manifesting hysteresis characteristics.
FIGS. 1(a) and 2(a) show examples of the inverter type CMOS input buffer and the hysteresis input buffer, respectively. FIG. 1(a) shows a circuit of a conventional inverter type CMOS input buffer and FIG. 1(b) shows a characteristic curve of the input/output of the buffer of FIG. 1(a).
As shown in FIG. 1(a), the inverter type CMOS input buffer includes first and second CMOS inverters INV1 and INV2. These inverters INV1 and INV2 are connected in series to each other wherein the inverter INV1 represents the input stage of the buffer and the inverter INV2 represents the output stage of the buffer. The CMOS inverter INV1 includes a PMOS transistor Q1 and an NMOS transistor Q2 connected in series with their drains connected to an output node N1. A supply voltage VDD terminal is coupled to the source of the PMOS transistor Q1, and the source of the NMOS transistor Q2 is grounded by the ground voltage VSS terminal. Although not shown in the drawings, the CMOS inverter INV2 has the same configuration as the inverter INV1.
When an input signal IN transiting from a high level to a low level is input to the buffer, the PMOS transistor Q1 is turned on and a current path is established between the supply voltage VDD terminal and the output node N1. The current supplied by the supply voltage VDD raises the voltage of the output node N1 and the voltage at the node N1 is inverted by the inverter INV2. With a low level input signal IN, the buffer generates a low level output signal OUT.
When the input signal IN transits from a low level to a high level, the PMOS transistor Q1 is turned off, the NMOS transistor Q2 is turned on, and a current path is established between the output node N1 and the ground terminal. Current flows to the ground terminal and decreases the voltage VN1 at the output node N1. At this time the input signal IN is in a high level and the voltage VN1 is in a low level. The low level node voltage VN1 is inverted by the inverter INV2. As a result, with a high level input signal IN, the buffer generates a high level output signal OUT. The input signal IN and the output signal OUT of the conventional buffer in FIG. 1(a) then have the same voltage levels at a given time.
Depending on the threshold levels of the CMOS transistors used in the conventional input buffer, the logical value of the input signal changes. Parameters for setting the threshold levels of conventional CMOS transistors include a high level input voltage VIH and a low level input voltage VIL. The high level input voltage VIH is defined to be the minimum value of a voltage range recognized by a CMOS inverter as the high level. The low level input voltage VIL is defined to be the maximum value of a voltage range recognized by a CMOS inverter as the low level.
In the input/output characteristic curve shown in FIG. 1(b), the high level input voltage VIH and the low level input voltage VIL for the conventional buffer as shown in FIG. 1(a) are located where the input voltage VIN has the unity gain of one (1). The input voltage VIN is the voltage of the input signal IN.
A further discussion on the operation of the conventional CMOS inverter INV1 in accordance with the parameters VIH and VIL is as follows.
When the level of the input voltage VIN is between the low level input voltage VIL and the ground voltage, the node voltage VN1 becomes high and is input to the CMOS inverter INV2. When the level of the input voltage VIN is between the high level input voltage VIH and the supply voltage VDD, the voltage VN1 becomes low and is input to the inverter INV2. The inverter IN2 inverts the voltage VN1 to generate the output signal OUT.
By properly setting the values of the low and high level input voltages VIL and VIH in both CMOS inverters INV1 and INV2, the output voltage range of the CMOS inverter INV1 can be modified in accordance with the voltage range allowed by the CMOS inverter INV2. However, if noise is provided to these CMOS inverters so that the input voltage level VIN fluctuates, the voltage VIN also fluctuates and an unstable output signal OUT is generated from the CMOS inverter INV2. For example, if the input voltage VIN is slightly lower than or equal to the low level input voltage VIL and noise is mixed into the voltage VIN to momentarily increase the voltage VIN to a level higher than the voltage VIL, an undesired low level (instead of a high level) voltage VN1 and a high level output signal OUT will be generated. That is, with a low level input voltage VIN, a high level output signal OUT is generated which is contrary to the expected output level. Therefore, the conventional inverter type CMOS input buffer as described above has a problem of instability for use in integrated circuits (ICs) which require extremely high reliability.
In order to solve this problem of noise in the conventional inverter type CMOS input buffer, an input buffer having hysteresis characteristics is used. FIG. 2(a) shows a circuit of a conventional hysteresis input buffer and FIG. 2(b) shows hysteresis curves for the input/output of the buffer shown in FIG. 2(a).
As shown in FIG. 2(a), a conventional hysteresis input buffer includes a CMOS inverter INV3 at the input stage and a CMOS inverter INV4 at the output stage. The CMOS inverter INV3 includes a PMOS transistor Q3 and an NMOS transistor Q4 connected to each other in series wherein the supply voltage VDD is applied to the PMOS transistor Q3 and the NMOS transistor Q4 is connected to the ground voltage VSS. The CMOS inverter INV3 also includes a PMOS transistor Q5 and an NMOS transistor Q6 which are connected to each other in series, similar to the structure of PMOS and NMOS transistors Q3 and Q4. The transistors Q3 and Q4 are connected in parallel with the transistors Q5 and Q6 between the supply voltage VDD terminal and the ground voltage VSS terminal. All the drains of the transistors Q3-Q6 are connected together at an output node N2.
The gates of the PMOS and NMOS transistors Q3 and Q4 are controlled by the input signal IN and the gates of the PMOS and NMOS transistors Q5 and Q6 are controlled by the output signal OUT of the CMOS inverter INV4. In other words, the hysteresis characteristic is implemented by controlling the PMOS and NMOS transistors Q5 and Q6 with a feedback output signal of the CMOS inverter INV4.
As shown in FIG. 2(b), the characteristic curve (1) is realized by selectively turning on the transistors Q3 and Q4 only, which is equivalent to the circuit of FIG. 1(a). The characteristic curve (2) is realized when the input voltage VIN transits from a high level to a low level, and the characteristic curve (3) is realized when the input voltage VIN transits from a low level to a high level.
When the input voltage VIN is in a low level (VIN.ltoreq.VIL), the NMOS transistor Q4 is turned off and the PMOS transistor Q3 is turned on, whereby a current path is established between the supply voltage VDD terminal and the node N2. Voltage at the node N2 (i.e., VN2) increases to a high level by the current from the voltage VDD terminal and the CMOS inverter INV4 inverts the high level voltage VN2 to a low level output signal OUT. The low level output signal OUT is then fed back to the inverter INV3, turning on the PMOS transistor Q5 and turning off the NMOS transistor Q6. The turned-on PMOS transistors Q3 and Q5 establish a current path between the voltage VDD terminal and the output node N2.
In this state, if the input voltage VIN transits from the low level to a high level and fluctuates to a level higher than the high level input voltage VIH, the PMOS transistor Q3 is turned off and the NMOS transistor Q4 is turned on. Since the PMOS transistor Q5 was already turned on by the previous output signal OUT, a current path is created between the supply voltage VDD terminal and the ground VSS terminal through the transistors Q4 and Q5.
Here, the amount of current provided to the node N2 is determined by the current driving capabilities of the transistors Q4 and Q5. If the NMOS transistor Q4 and the PMOS transistor Q5 have the same current driving power (i.e., they have the same W/L (width/length) ratio of the channel), the amount of current provided to the node N2 through the PMOS transistor Q5 and to the ground through the NMOS transistor Q4 become the same such that the node voltage VN2 equals VDD/2. If the current driving capability of the pull down transistor, e.g., the NMOS transistor Q4 or Q6, is higher than that of the pull up transistor, e.g., the PMOS transistor Q3 or Q5, the potential at the node N2 can be pulled down.
If the input voltage VIN is higher than the high level input voltage VIH2 of the characteristic curve (3) in FIG. 2(b), the node voltage VN2 will be below than the logical threshold voltage of the CMOS inverter INV4. As a result, a high level output signal OUT is generated to turn on the NMOS transistor Q6 and the current driving capability of the pull down transistor improves.
In this state, if the input voltage VIN transits from the high level to a low level and becomes lower than the low level input voltage VIL, the PMOS transistor Q3 is turned on and the NMOS transistor Q4 is turned off. Since the NMOS transistor Q6 was already turned on by the output signal OUT, the drain current of the NMOS transistor Q6 equals the drain current of the PMOS transistor Q3. A current path between the supply voltage VDD terminal and the ground is created through the transistors Q3 and Q6 and the node voltage VN2 remains at VDD/2
If the input voltage VIN decreases continuously and is lower than the low level input voltage VIL1, the amount of current supplied to the node N2 through the PMOS transistor Q3 becomes larger than the amount of current provided to the ground through the NMOS transistor Q6. This raises the node voltage VN2 as shown in FIG. 2(b).
If the node voltage VN2 is raised continuously and is greater than the logical threshold voltage of the CMOS inverter INV4, the output signal OUT transits to a low level. This turns on the PMOS transistor Q5 and turns off the NMOS transistor Q6. At this time, both PMOS transistors Q3 and Q5 are turned on. Therefore, current provided from the supply voltage VDD terminal through the PMOS transistors Q3 and Q5 increases extremely rapidly which raises the node voltage VN2.
As discussed hereinabove, when the input voltage VIN transits to a high level, the node voltage VN2 follows curve (3) in FIG. 2(b) with parameters of low and high level input voltages VIL2 and VIH2. When the input voltage VIN transits from a high level to a low level, the node voltage VN2 follows curve (2) with parameters of low and high level input voltages VIL1 and VIH1. The curve (1) is realized by selectively turning on the transistors Q3 and Q4. The conventional input buffer of FIG. 2(a) manifests the hysteresis characteristic as shown in FIG. 2(b).
Since the hysteresis characteristic of the conventional input buffer changes the ranges of the low and high level input voltages depending on the direction of transitions in the input signal (i.e., high to low level, or low to high level), the conventional hysteresis input buffer offers a large noise resistance margin. At the same time, however, a large swing width of the input voltage VIN results in realizing this hysteresis characteristic. This increases the transfer time of the input and output signals such that a high speed input/output operation can not be carried out using the above-described conventional hysteresis input buffer. Therefore, an input buffer with a superior noise resistance which is capable of conducting high speed operations is needed for use in semiconductor integrated circuits requiring high stability and high speed operations.